MINILOG 4.5 by W.M.J. de Valk. ================================ Minilog is a convenient aid for the automated design of digital function blocks, intended for educational purposes. The package consists of a number of subprograms, controlled by one common user interface. It runs on an MSDOS PC or on HP-UX workstations. The input is either a boolean function table or a tabular state machine description. The output can be obtained in tabular format, as logic equations, a FAULTSIM netlist, an ABEL input file or a schematic diagram for COMPASS on HP-UX workstations or on a PC either for AutoCAD or ORCAD, depending on the installation. The input function is checked for errors and completeness, minimized either in multiple- or in single-output mode using the Espresso algorithm and converted into the required output format. The result is a two-layer sum-of-products or a product-of-sums description of the on- or off-cover. ___________________________________________________________________________ | | | NOTE: Command line switches on an MSDOS PC are indicated with a slash (/) | | instead of the dash (-) on the HP-UX workstations. So replace the | | dashes in the document below by slashes for the PC-version. | | All switches must appear separately, separated by blank spaces. | |___________________________________________________________________________| Command line syntax. ==================== minilog [option-switch] [ input file [ D | T | RS | JK ] ] NOTES: - [] Is optional, | means either/or. - The flipflop implementation specification is disregarded if no STATES line is present in the input file or an ABEL input file is being generated. Options. ======== A number of options may be selected with switches, placed immediately after the program call on the command line. On MSDOS PC's the dashes (-) must be replaced by slashes (/). Minimization options -s The minimization is performed in single-output mode. In version 4.X this is rather time consuming as each output function is separately handled. This mode should be used if a PAL-implementation is required, while the PLA-implementation requires the default multiple-output minimization. -m The multiple output implementation of the state machine outputs will be guaranteed to be of the MOORE-type if so specified. -p Lets the program produce a product-of-sums result instead of the usual sum-of-products. -o The OFF-cover will be minimized instead of the default ON-cover. Output format options -e Produces a minimized result in the form of logic equations instead of the usual tabular format. Recommended to novice users only for reason of table interpretation. -f The minimization result is translated into a FAULTSIM netlist. The design correctness can thus easily be verified, using FAULTSIM in functional mode (using -n switch). The netlist can be incorporated into a hierarchical structure, that must be expanded with FSEXPAND prior to simulation. The -f switch may optionally be followed by a library specification and/or an extension of 1 or 2 characters that will be concatinated to the internal netlist nodes. Formats: -f: -f:/ -f:/ -d The minimization result is converted into a schematic diagram with a belonging symbol. A library must be specified. Format: -d: On HP-UX workstations a COMPASS .la-file is generated, while on a PC either AutoCAD script files .sch and .sym for schematic and symbol are generated or an ORCAD macro file .sch, depending on the installation. -a The minimization result is converted into an input file in ABEL-format, for implementation in a logic array. The flipflop type specification is ignored, as this is handled by ABEL depending on the device type. Implementation directives -i Use inverting gates for the generation of netlists or schematics, only in conjunction with the -f or -d switches. -r In generated schematic drawings or Faultsim netlists (-d or -f switch) the state register outputs are added to the primary outputs. Entering combinational function tables. ======================================= The input for the simulater is a textfile, composed with any ASCII editor. Allowed separators are any combinations of white spaces, comma's, semicolons (;) or vertical bars (|). No distinction is made between uppercase and lowercase characters. The first line should contain the reserved word 'TABLE' followed by the name of the function table to be minimized. The next lines contain the names of the primary inputs and outputs of the network, starting with the reserved words 'INPUT' or 'OUTPUT'. Both input and output variables are limited to a number of 40, more than one INPUT or OUTPUT line is allowed. The length of the input and output names is limited to 8 characters, for the generation of netlists or schematics with the -f or -d switches it is strongly recommended to limit those identifiers to no more than 6 characters. If the function must be implementated in a PLD some directives concerning the device type and the pin assignment to ABEL can be placed immediately after the INPUT and OUTPUT lines, all starting with #. These ABEL directives are ignored for all other output formats. The following lines consist of input vectors and output vectors, each with a length matching the specified number of input and output variables. To improve the readability of the table the bits may be separated from eachother with comma's, semicolons, vertical bars, tabs and blanks. The identification of the variables is straight forward in the same order as they are specified in the input and output lines. Unspecified variables in the input vector and don't cares in the output vector are denoted by a dash (-). If a product term has no meaning for an output function (not a don't care!!) it is denoted by a period (.) in the output vector field. Empty lines are ignored, comment lines starting with double quotes (") are copied onto the screen and into the output file. Comment placed after the input and output vectors is allowed as well. The last line contains the word 'END'. The minimized table specifies all essential product terms (factors in case of product of sums minimization) and the output functions in which they are active. An example is given in the file "bcd_7seg.tbl"; it can be optimized with the command line: "minilog bcd_7seg". table bcd-7segment_decoder input qd qc qb qa output a b c d output e f g " ABEL device and pin assignment lines starting with # # device p16L8 " for ABEL output format only # pins 1=qd 2=qc 3=qb 4=qa " for ABEL output format only # pins 12=a 13=b 14=c 15=d " for ABEL output format only # pins 16=e 17=f 18=g " for ABEL output format only 0000 , 1 1 1 1 1 1 0 0001 , 0 1 1 0 0 0 0 0010 , 1 1 0 1 1 0 1 " -- a -- 0011 1 1 1 1 0 0 1 " | | 0100 ; 0 1 1 0 0 1 1 " f b 0101 ; 1 0 1 1 0 1 1 " | | 0110 ; 0 0 1 1 1 1 1 " -- g -- 0111 1 1 1 0 0 0 0 " | | 1000 1 1 1 1 1 1 1 " e c 1001 | 1 1 1 0 0 1 1 " | | 101- | - - - - - - - " -- d -- 11-- | - - - - - - - end The minimized result is: MINIMIZATION RESULT STATISTICS ============================== FOUND 9 ESSENTIAL PRODUCT TERMS MAXIMUM FANIN: 7 TOTAL LITERAL COUNT: 50 MAXIMUM PRODUCT TERM SIZE: 3 MAXIMUM OUTPUT FUNCTION SIZE: 5 ============== QQQQ DCBA ABCDEFG ============== --10 | ...11.. -1-0 | ..1..11 -0-0 | 1..11.. --00 | .1...1. -00- | .11.... -101 | 1.11.11 -01- | .1.1..1 --11 | 111.... 1--- | 1....11 The above table translated into logic equations: A = QC'.QA' + QC.QB'.QA + QB.QA + QD B = QB'.QA' + QC'.QB' + QC'.QB + QB.QA C = QC.QA' + QC'.QB' + QC.QB'.QA + QB.QA D = QB.QA' + QC'.QA' + QC.QB'.QA + QC'.QA E = QB.QA' + QC'.QA' F = QC.QA' + QB'.QA' + QC.QB'.QA + QD G = QC.QA' + QC.QB'.QA + QC'.QB + QD With the -e option the output can be presented in the form of logic equations. Writing all signal names in full, however, would lead to very long, badly arranged expressions. Therefore the variables are indicated with singular characters, the inputs from 'A' and the outputs up to 'Z'. This limits the total number of input plus output variables to 26. The minimized equations are preceded bij a variable translation table. Example: "minilog -e bcd_7seg" MINIMIZATION RESULT STATISTICS ============================== FOUND 9 ESSENTIAL PRODUCT TERMS MAXIMUM FANIN: 7 TOTAL LITERAL COUNT: 50 MAXIMUM PRODUCT TERM SIZE: 3 MAXIMUM OUTPUT FUNCTION SIZE: 5 INPUT SIGNAL | OUTPUT SIGNAL REPRESENTATION A : QD | T : A X : E B : QC | U : B Y : F C : QB | V : C Z : G D : QA | W : D MINIMIZED EQUATIONS T = B'D' + BC'D + CD + A U = C'D' + B'C' + B'C + CD V = BD' + B'C' + BC'D + CD W = CD' + B'D' + BC'D + B'C X = CD' + B'D' Y = BD' + C'D' + BC'D + A Z = BD' + BC'D + B'C + A The -f option can be used to obtain a FAULTSIM netlist, a convenient way to verify the design correctness. The -f option is not compatible with the -e, -a and -d options. Be sure that the first 6 characters of the identifiers indicate the input and output variables uniquely, to avoid problems during the FAULTSIM execution. Using identifiers containing more than 6 characters will give rise to a warning. Optionally a library can be specified, in order to determine the maximum number of gate inputs. Use the same library as with the -d option for the netlist to be identical to the schematic. Format: -f: An optional extension of maximally 2 characters may be specified, that will be concatinated to all internal nodes within the netlist. This will uniquely identify the internal nodes of any logic network. Format: -f:[library]; Example: "minilog -f bcd_7seg" NETLIST BCD-7SEGMENT_DECODER " Generated by Minilog on Monday, May 15, 1989; 15:31 INPUT QD QC QB QA OUTPUT A B C D E F G N_QD INV QD N_QC INV QC N_QB INV QB N_QA INV QA NET1 AND QB N_QA NET2 AND QC N_QA NET3 AND N_QC N_QA NET4 AND N_QB N_QA NET5 AND N_QC N_QB NET6 AND QC N_QB QA NET7 AND N_QC QB NET8 AND QB QA NET9 BUF QD A OR NET3 NET6 NET8 NET9 B OR NET4 NET5 NET7 NET8 C OR NET2 NET5 NET6 NET8 D OR NET1 NET3 NET6 NET7 E OR NET1 NET3 F OR NET2 NET4 NET6 NET9 G OR NET2 NET6 NET7 NET9 END If one of the schematic interfaces is installed, the -d switch can be used to obtain a schematic diagram. The specification of a library is required. This library file contains information regarding the gates, like e.g. the number of inputs, the topological symbol data and the names, must have an extension ".lib" and should reside in the MINILOG executable directory. Formats: -d: or -d where is the desired library file without extension. The -d option can't be combined with the -e, -f and -a options. In addition to either the -f or the -d switches with the -i switch the generated netlist or schematic can be optimized in terms of speed and space by using as many inverting gates as possible. The result remains, however, a two layer implementation of the logic circuit. Using the -a switch an ABEL input file is generated with extension .abl, that contains all required information for the PLD-implementation of the design if immediately after the INPUT and OUTPUT lines the device-type is specified and all pins assigned. Of course the ABEL file can be edited afterwards. The -a option can't be combined with the -e, -f and -d options. Entering state transition tables. ================================= Like the function tables, the input file must start with the 'TABLE' and optionally the 'INPUT' and 'OUTPUT' lines, optionally followed by the ABEL device and pin assignment lines. These ABEL directives must include the flipflop output names "Qi" with i ranging from 0 to the state vector length minus 1, the clock pin "FF.CLK" and if applicable the asynchronous reset pin "FF.AR". If the device, that is being used, contains other flipflop control signals, the generated ABEL input file has to be completed afterwards by editing it. The following line should contain the word 'STATES', after which the state table follows. This table records the state symbols and the belonging binary state code. The state symbol is an identifier with a maximal length of 4 characters. Again no distinction is made between uppercase and lowercase characters. The code is entered with the most significant bit first. Specification of don't care states may be necessary for an optimal result. Empty lines or lines starting with double quotes (") are treated as comment in a similar way as above. The states table is completed with an 'END' line, after which the state transition table follows, completed with 'END' as well. A line consists of the prior state symbol followed by an optional input vector and the next state symbol with an optional output vector. The state-register element names QN...Q0 cannot be used as output signal name. If the state register output is required as primary circuit output, as is usually the case for counters, the -r switch must be used combined with the -f or -d switch. In the case of the default multiple-output minimization a MOORE-type state machine might be turned into a MEALY-type. The primairy output function remains, however, independent of the primary inputs, but the multiple-output minimization may introduce some dynamic dependence. Use the -m switch whenever a MOORE-type result must be guaranteed. All switches, documented above for the combinational functions, can be used for state machines as well. Having recognized the STATES line, the program will ask the flip-flop type to be used. The excitation vectors belonging to the desired state transitions are automatically generated. The flipflop outputs are indicated with 'Q', the inputs with '_D', '_T', '_J', '_K', '_S' or '_R', followed by the order number. Don't use these identifiers in the list of primary inputs or outputs. The state expansion must not lead to more than 40 input or output variables in the excitation table. An example is found in the file "counter.tbl". Try a minimalisation with several types of flip-flops and notice the difference in the complexity of the logic circuits needed to realise the counter. table counter input enab up output co " ABEL device and pin assignment lines starting with # # device p22v10 " for ABEL output format only # pins 3=enab 4=up 17=co " for ABEL output format only # pins 14=Q2 15=Q1 16=Q0 " flipflop outputs Qn-1 ... Q0 # pins 1=FF.clk 2=FF.ar " clock and asynchronous reset states qa 000 qb 001 qc 010 qd 011 qe 100 qx 101 qy 11- qz --- end qa 0- qa 0 qa 11 qb 0 qa 10 qe 1 qb 0- qb 0 qb 11 qc 0 qb 10 qa 0 qc 0- qc 0 qc 11 qd 0 qc 10 qb 0 qd 0- qd 0 qd 11 qe 0 qd 10 qc 0 qe 0- qe 0 qe 11 qa 1 qe 10 qd 0 qx -- qz - qy -- qz - end Running the program. ==================== Running the program without command line parameters will have you asked some questions that are self-explanatory. You can, however, enter the demanded data on the command line in the same order as they would be asked for, as already is described before. All option selection switches must immediately follow the program call. Modification history. ===================== 4.0 The minimization algorithm is now Espresso. The -s switch has been temporary disabled, the -o switch added. The number of input and output variables has been increased to 40. A PC-version has not been released, the only supported platform for the time being is the APOLLO workstation. The -n switch has no meaning anymore, and has been omitted. 4.1 The -s switch has been reenabled, the -m and -d switches have been added and the -f switch has been modified, in order to assure that the netlist can be made identical to the schematic diagram obtained with the -d switch. Also a PC-version has become available. 4.2 The -i switch has been introduced. 4.3 The number of library gate-inputs may now be different for inverting gates with respect to non-inverting. The separator ";" within the -f switch, for adding up to two characters to the internal net names, has been replaced by "/", as the first is intercepted by the UNIX command-line interpreter. 4.4 The -r switch has been introduced. A scanpath can be included in the generated schematics. Internal signal names like 'D' and 'T' have been replaced by '_D' and '_T'. Flipflop control inputs RST, PRST, CLK and TSTM can be set to high or low active (prefix N) in the library files. The -p and -o switches don't exclude eachother anymore. The maximum input line length has been increased from 80 to 255 characters. The PC-version has been interfaced to both Autocad and Orcad for schematics generation. The PC screen mode remains now unmodified while running Minilog. A bug has been corrected that sometimes created incorrect schematics and netlists while using both -i and -o options. The HP-UX version with a COMPASS interface became available. 4.5 (4.50): The APOLLO version is not supported anymore. The -a switch has been incorporated. More complete minimization statistics are being presented from now on. A bug has been corrected that caused a hangup if Minilog was started with command line options only. Remarks. ======== In the public-domain an MS-DOS version of this program is available (PC-version 4.50), of which the unmodified code can be freely used, copied and distributed for non-commercial educational purposes only. All other rights are strictly reserved by the author. Relevant remarks and sugestions are highly appreciated, and should be addressed to: W.M.J. de Valk, Hogeschool Eindhoven, Sector TO, afd E, Postbus 347, 5600 AH Eindhoven, The Netherlands. Email: W.deValk@fontys.nl References. =========== As literature any recent introductory textbook on structured design methodology for logic systems is recommended. Some examples: ( Author, Title, Publisher, ISBN ) Almaini A, Electronic Logic Systems, Prentice/Hall (UK), 0-13-251752-3 Lewin D, Design of Logic Systems, Van Nostrand Reinhold (UK), 0-442-30606-7 Valk Wim de, Leerboek ASIC's - Digitale Systemen, Addison Wesley (NL), 90-6789-399-4.